It is well known to produce FeRAM capacitors with a COP (capacitor on plug) structure. The capacitor is fabricated from a bottom electrode layer, a ferroelectric layer, and a top electrode layer. These layers are formed on a substructure having other electronic components in lower levels, and a plug of conductive material extends upwards from the other components, for electrical connection to the bottom electrode of the capacitor. Between the top of the plug and the bottom electrode layer are located one or more conductive barrier layers of IrO2 and/or Ir (for example layers in the sequence IrO2/Ir/Ir), for preventing diffusion of gases between the bottom electrode and the plug.
Hardmask elements, typically formed Tetraethyl Orthosilicate (TEOS), are deposited over the top electrode layer, and used to etch the structure so as to remove portions of the bottom electrode layer, ferroelectric layer, and top electrode layer which are not under the hardmask elements. The etching separates the top electrode layer into top electrodes, the bottom electrode layer into bottom electrodes, and the ferroelectric layer into ferroelectric elements sandwiched by respective pairs of top electrodes and bottom electrodes. This etching can be carried out in multiple stages, for example a first stage using a first set of hardmask elements in which the top electrode layer and ferroelectric layer are etched, and a second stage in which a second set of hardmask elements are deposited and used to etch the bottom electrode layer.
Two moments of this process are shown respectively in FIGS. 1(a) and 1(b). FIG. 1(a) shows a moment in which top electrode elements 1 (formed using first hardmask elements 2) and ferroelectric elements 3 (e.g. of PZT (lead zirconate titanate)), have been formed over a bottom electrode layer 5 of Pt. The bottom electrode layer 5 is itself formed over an IrO2 layer 7, which is over an Ir/Ir layer 9 (the Ir/Ir layer 9 is in fact a stack of two separate layers). The Ir/Ir layer 9 covers a substructure having a TEOS matrix 11 through which plugs 13 of conductive material extend. The plugs 13 electrically connect the bottom electrode layers 5 (via the conductive barrier layers 7, 9) to further electronic elements (not shown) in lower levels of the structure. At the moment shown in FIG. 1(a), a TEOS layer 15 has just been deposited. Subsequently second hardmask elements 17 are formed over it, and as shown in FIG. 1(b) the structure is then etched to remove the portions of the bottom electrode layer 5 and barrier layers 7, 9 which are not beneath the second hardmask elements 17. Thus the bottom electrode layer 5 is divided into individual bottom electrode elements 19 which are connected by respective plugs 13 to respective sets of the further electronic elements (not shown). As shown in FIG. 1(b) there are two top electrode elements 1 and ferroelectric elements 3 per bottom electrode element 19, but this feature need not be present.
FIG. 1(b) illustrates two problems with this process. Firstly, the thick barrier layers 7, 9, when etched, form Ir/IrO2 fences 21 on the sides of the ferrocapacitors. Secondly, damage 23 can occur to the ferroelectric elements 3 (especially at their sides), which reduces the parameter Qsw (the ferroelectric material capacitor charge difference between the polarization of the material when it is switched and without being switched). It is believed that this damage is caused by Ir and IrO2 diffusing through the Pt bottom electrode layer 5 (e.g. during the processes which are performed to etch the top electrode layer and ferroelectric layer and/or the processes which are performed to etch the bottom electrode layer 5).
Recently, the article “4 Mbit embedded FRAM for high performance system on Chip (SoC) with large switching charge, reliable retention and high imprint resistance” by Y. Hofi, Y. Hikosaka, A. Itoh, K. Matuura, M. Kurasawa, G. Komuro, K. Muruyama, T. Enshita and S. Kashiwagi, published in the proceedings of IEDM 2002, appears to disclose a structure in which the Ir barrier element is recessed. However, in this case the barrier elements will be less able to prevent oxygen diffusion to the plug.